Embodiments of the inventive concepts relate to a method for correcting a mask layout designed for fabrication of a photomask and a method of fabricating a semiconductor device using the same.
A photomask may be used to print an integrated circuit layout on a wafer in a photolithography process used for fabrication of a semiconductor device. Generally, the photolithography process may use a method of transferring mask patterns formed on the photomask to the wafer through an optical lens. The photomask may include a transparent region and an opaque region. The transparent region may be formed by etching a metal layer disposed on the photomask and may transmit light. On the other hand, the opaque region may not transmit light. The mask patterns may be formed by the transparent region and the opaque region. Light emitted from a light source may be irradiated to the wafer through the mask patterns of the photomask, and thus the integrated circuit layout may be printed on the wafer.
As an integration degree of a semiconductor device increases, the mask patterns of the photomask become closer to each other and a width of the transparent region becomes much narrower. Due to this proximity, interference and diffraction of light may occur, and thus a distorted layout different from a desired layout may be printed on the wafer. Optical proximity correction may be performed to prevent the distortion of the layout caused by these optical effects. In addition, process proximity correction may be performed to compensate distortion of the layout caused by a non-optical effect such as a process variation in a fabricating process of a semiconductor device.
The optical proximity correction and the process proximity correction may be performed based on a photolithography simulation that predicts a contour image to be formed on the wafer from a designed mask layout and a critical dimension (CD) of the contour image.